High-speed processor-based electronic systems have become all-pervasive in computing, communications, and consumer electronic applications to name a few. The pervasiveness of these systems, many of which are based on multi-gigahertz processors, has led in turn to an increased demand for high performance memory systems. As one example, FIG. 8 is a block diagram of a high performance memory system 800 under the prior art. This memory system 800 includes a memory controller 802 coupled to one or more memory component(s) 804. The memory controller 802 includes address circuitry 812 to drive address/control information outputs and write data circuitry 822 to drive write data information outputs to the memory component(s) 804.
Information is carried on signal paths between the memory controller 802 and the memory component(s) 804 by a signal, where the signal includes a symbol (such as a bit) that propagates along the signal path. The symbol is present at a particular point on the signal path for a characteristic time, called the symbol interval or symbol time. A signal path is typically composed of a conductive interconnect. A signal path may use one or two (or more) interconnects to encode the signal, along with return paths through adjacent power conductors.
The memory system 800 uses a variety of signals to couple the memory controller 802 and the memory component(s) 804. One set of signals are address/control signals A and the corresponding timing signals TA (also referred to as address/control timing signals TAX). The address/control signals A carry address and control information, and are labeled as A0, A1, and A2 to show the address/control signals at different points along the signal path between the memory controller 802 and the memory component(s) 804. The timing signals TA carry timing information that indicates when information is valid on the address/control signals A. The timing signals are labeled as TA0, TA1, and TA2 to show the timing signals at different points along the signal path between the memory controller 802 and the memory component(s) 804.
Another set of signals that couple the memory controller 802 and the memory component(s) 804 are write data signals W and the corresponding data valid or timing signals TW (also referred to as write data valid signals or write data timing signals TW). The write data signals W carry write data information, and are labeled as W0, W1, and W2 to show the write data signals at different points along the signal path between the memory controller 802 and the memory component(s) 804. The timing signals TW carry timing information that indicates when information is valid on the write data signals W. The timing signals are labeled as TW0, TW1, and TW2 to show the timing signals at different points along the signal path between the memory controller 802 and the memory component(s) 804. Note that the label for address/control timing signal TAO is shortened to T0 in the memory system 800, and likewise, the label for write data timing signal TWO is shortened to T0 because the address circuitry 812 and the write data circuitry 822 operate within a common timing domain in the memory controller 802.
The timing signals TA and TW carry timing information in the form of events, such as a transition between two symbol values (such as a rising edge). A timing signal indicates when valid information is present on a set of related signals. Each timing event may be related to one symbol on each signal of the set, or it may be related to more than one symbol on each signal. The timing signal may only have timing events when there are valid symbols on the associated set of signals, or it may have timing events when there are no valid symbols. Consequently, each bit on the address/control signal A is associated with a timing event on the corresponding address timing signal TA (a rising edge for example). Similarly, each bit on the write data signal W is associated with a timing event on the write data timing signal TW.
The address and control information A2 is received at the memory component(s) 804 with the timing signal TA2, and is coupled to the core circuitry 814 of the memory component(s) 804. This core circuitry 814 operates in the TA2 timing domain. The TA2 timing domain is delayed from the T0 timing domain of the memory controller 802 by the propagation delay time tPD-A (the time required by the signals at A1 and TA1 to propagate to A2 and TA2, respectively).
Further, the write data information W2 is received at the write circuitry 824 of the memory component(s) 804 with the timing signal TW2. The write circuitry 824 operates in the TW2 timing domain, where the TW2 timing domain is delayed from the T0 timing domain of the memory controller 802 by the propagation delay time tPD-W (the time required by the signals at W1 and TW1 to propagate to W2 and TW2, respectively).
In writing data to the core circuitry 814 of the memory component 804, write data received at the write circuitry 824 (TW2 timing domain) must be transferred to the core circuitry 814 (TA2 timing domain). This transfer is accomplished by the interface circuitry 834, where the interface circuitry 834 compensates for timing differences between the TW2 timing domain and the TA2 timing domain (determined by taking the difference between tPD-A and tPD-W propagation delay times). The interface circuitry 834 typically compensates for timing differences between the TW2 timing domain and the TA2 timing domain of approximately +/−tDQSS (data sheet term representing system offsets and pin-to-pin offsets in a dynamic random access memory (DRAM)). Therefore, if the value of tDQSS is made large, it relaxes the signal path matching constraints imposed on tPD-A and tPD-W, but increases the burden on the interface circuitry 834 to resolve timing discrepancies between the different timing domains.
If however the value of tDQSS is reduced in order to reduce the burden on the interface circuitry 834, it increases the signal path matching constraints imposed on tPD-A and tPD-W. Typically, the A and TA signal paths must be routed together and matched relatively tightly so the timing information on TA can be used to reliably sample the address and control information on the A signals. Similarly, the W and TW signal paths must be routed together and matched relatively tightly so the timing information on TW can be used to reliably sample the address and control information on the W signals. Thus, if the tDQSS value is made small, the tPD-A and tPD-W values of all the A/TA and W/TW signals must be simultaneously matched.
FIG. 9 is a timing diagram 900 showing signals for a write operation in the memory system 800 under the prior art. Address/control information, “addr,” is placed on the address/control signal A0 by the memory controller in response to the first rising edge of the T0 timing signal. The address/control signal A0 is then driven onto the signal path as the A1 signal along with a rising edge of the corresponding TA1 signal. The A1 and TA1 signals propagate to the core circuitry of the memory component and become the A2 and TA2 signals at time tPD-A later.
Additionally, write data is placed on the write data signal W0 by the memory controller in response to the first rising edge of the T0 timing signal. The write data signal W0 is held in the memory controller for a time tWL (where tWL is a fixed delay of two (2) cycles or periods for example) before being driven onto the W1 signal (along with a rising edge of the corresponding TW1 signal). The W1 and TW1 signals propagate to the write circuitry of the memory component and become the W2 and TW2 signals at time tPD-W later.
The write operation in the memory system 800 results in a mismatch between the timing of the TA2 and TW2 timing signals at the memory component(s). In order for the interface circuitry to compensate for this timing mismatch, the magnitude of the mismatch must not exceed the difference between the value tDQSS and the value tWL (the quantity (tDQSS-tWL)); when the mismatch exceeds the difference between the value tDQSS and the value tWL the write data cannot be reliably transferred from the write circuitry to the core circuitry within the memory component. Consequently, there is a need in high performance memory systems to increase the reliability and accuracy of data writes to memory components while relaxing the signal path matching constraints (relating to the tPD-A and tPD-W values) and reducing the burden on the interface circuitry.